The present invention relates to the field of memory device generators for the generation of memory devices in a Computer Aided Design (CAD) environment. More particularly, the invention is directed to a memory device generator for generating memory devices with redundancy.
It is known that in the field of complex integrated circuits manufacturing CAD tools have been developed to facilitate and speed up the designers"" job. Such tools make use of libraries of standard, predefined circuit components and/or building blocks (e.g., logic gates, elementary memory cells, etc.), and generally comprise device generators that interact with the user and the predefined component libraries to generate a resultant complex integrated circuit satisfying the user""s needs.
In particular, memory device generators operating in CAD environments have been developed that allow the user to generate a memory device, either stand-alone or to be embedded in a more complex integrated circuit, starting from predefined basic building blocks such as the elementary memory cells. The user can specify the desired size of the memory device to be generated, as well as other parameters. The memory device generator is capable of generating memory devices of variable size.
A single port RAM generator is for example described in EP-A-600142, which is incorporated herein in its entirety by reference.
With respect to a full custom design approach, intended to optimize some aspects such as the silicon area occupation and the circuit speed, this design approach aims at reducing the design time.
Memory devices generated in this way suffer however of the same problems as conventional, fixed-size memories resulting from full-custom design approaches.
One of these problems is the possibility that the resulting memory device contains defective memory elements. In fact, due to the size of the memory cell array and manufacturing process yield problems, it could be desirable to generate a memory device with redundancy capability. This normally involves the provision of additional (i.e., redundant) memory rows and/or columns which, if no defects are present, are left unused, but in case of defects act as an extra memory to be used as a replacement for defective memory rows and/or columns.
During the device testing phase, if a defective memory cell is detected, the entire row or column to which the defective cell belongs is normally replaced by a redundant row or column.
In custom-designed, fixed-size memory devices the implementation of redundancy normally requires the provision of non-volatile memory registers for permanently replacing the defective cells.
Implementation of redundancy in a memory device automatically generated by means of a memory device generator poses problems. In fact, due to the unpredictability of the choices selectable by the user, who can usually specify the number of memory words, the word length (number of bits per word) and sometimes also the memory array aspect ratio (number of rows divided by the number of columns), the insertion by default of some predetermined number of redundant rows and/or columns may result in an inefficiently generated memory.
Additionally, since the memory registers normally used to implement redundancy have to be non-volatile, fuses or Unerasable Programmable ROM (UPROM) memory cells are normally used to form such registers. Integration of standard redundancy techniques in a memory device generator could complicate the manufacturing process of the automatically-generated memory device, because if for example the memory device to be generated is a RAM, integration of fuses or UPROMs memory cells can be achieved only by providing dedicated process steps.
In view of the state of the art described, it is an object of the present invention to provide a memory device generator to be used in a CAD environment capable of generating automatically memory devices with redundancy, overcoming the problems outlined above.
According to an embodiment of the present invention, such object is achieved by means of a memory device generator for generating memory devices in a CAD environment, the generator comprising:
a library containing predefined basic circuit components;
memory array generation interacting with said library for generating a variable-size memory array comprising a variable number of memory elements, and at least one redundant memory element;
memory element selection circuit generation means interacting with said library means for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to address inputs of the memory device;
wherein said memory element selection circuit generation means comprises means for generating a variable-size content-addressable memory means having a plurality of content-addressable memory locations each one associated with at least one respective memory element or with the at least one redundant memory element, each of said content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take said one value.
Thanks to the present invention, there is provided a memory device generator suitable for generating memory devices with redundancy capability, overcoming the problems of conventional redundancy techniques. This is made possible by the fact that the memory generator generates memory element selection circuits comprising content-addressable memory means, instead of conventional address decoder circuits. While in fact conventional address decoder circuits have a structure which is fixed once and for all during the design phase, a content-addressable memory can be easily reconfigured. If during testing a memory element is found defective, it can be replaced by a redundant memory element by simply storing in the content-addressable location associated with the redundant element the address configuration initially addressing the defective element.
These and other features and advantages of the present invention will be made more evident by the following detailed description of some embodiments thereof, illustrated as non-limiting examples in the annexed drawings, wherein: